The present invention relates generally to personal computers, also known as microcomputers. In particular, the present invention relates to an interface between the local bus of a personal computer (PC) and one or more data storage devices. The interface facilitates high speed data transfers (reads and writes) from the central processor of the PC over the local bus to the data storage devices. The present invention allows for faster data transfers than transfers through standard data storage interfaces that may be connected to the local bus or to the standard input/output expansion slots (ISA, EISA, and Micro Channel), generally found in PC architecture.
Personal computers can be characterized as single central processor devices. PCs have a single, multi-functional, general-purpose central processor (CPU) providing the computational power for the computer. The CPU is located on the motherboard which also includes other core logic chips and high speed memory (cache, DRAM). Although a PC is generally a single CPU device, a PC may include other devices called processors, e.g., math co-processors, processors on the keyboard and processors on disk drives. CPUs are made by a variety of manufacturers, including Intel Corporation, Advanced Micro Devices, and Motorola.
Since PCs first appeared in the 1970s, new generations of CPU have provided more computational power. This "power" can be identified by the increased clock speed of the devices, meaning that operations are being performed faster, and by wider buses (8-bit to 16-bit to 32-bit to 64-bit) that allow more data or instructions to be moved at a time. In order to fully realize the capability of the increasingly powerful CPUs, the related devices (memory, add-on cards, etc.) should operate at the same level.
For example, powerful CPUs need to access a certain amount of memory very quickly to fetch key instructions. This high speed memory (cache, DRAM) is located closest to the CPU, but has limited storage capacity (e.g., cache 1 Mbyte, DRAM typically 64 Mbytes but up to 256 Mbytes). Larger-capacity data storage devices, such as hard disk drives, serve as the primary data storage component of a PC. PC hard disk drives include several magnetic data storage disks and typically have up to 540 Mbytes of memory available (drive manufacturers are continuously developing larger capacity drives). Generally available PC-type hard disk drives have 16-bit data ports for data transfer and support a fixed sector size of 512 bytes.
Over time, there has evolved a hierarchy of needs for the CPU and a related hierarchy in the PC structure. In order to meet the most time-critical needs of the CPU, the concept of the local bus was implemented in PC architecture. In short, a local bus is a high-speed bus accessing a limited number of devices by direct addressing. The local bus provides cost and reliability advantages, a smaller power budget, and higher density packaging, in addition to its high speed performance. However, the local bus is not a general purpose expansion bus and does not allow for a large number of input/output connections. The term "local bus" also includes the concept of a "mezzanine" bus that is separate from the physical local bus of the CPU. Examples of such local bus interfaces are the VL-Bus.TM. and Peripheral Component Interconnect (PCI) bus. A general block diagram of the PCI bus is shown in FIG. 1.
As shown in FIG. 1, the local bus 1 can be conceptualized as a component interface for a limited group of I/O devices. There is another level of component or board interface, the standard expansion bus 2 (ISA, EISA, Micro Channel). The expansion bus 2 is the standard interface for additional data storage devices and add-on boards. The problem with using the expansion bus 2 for data read/write operations is that it is slow, i.e., it takes numerous clock cycles from the time the CPU signals the initiation of an operation before a data storage device on the expansion bus 2, such as a hard disk drive, is capable of completing the operation.
FIG. 2 is a timing diagram of a read or write operation from the CPU to a hard disk drive on the expansion bus showing the delay from the time the CPU places an address on the local bus until the time a disk drive connected to the expansion bus can complete the operation. At time t.sub.1, the CPU initiates an operation with an address (ADS#) strobe. Several clock cycles later, at time t.sub.2, the system address line (SA) shows that the address is valid on the expansion bus. Next, buffered address latch enable line (BALE) is asserted, starting the expansion bus cycle. At time t.sub.3 the command line (CMD) is asserted for several clock cycles, depending on the timing of the particular hard disk drive performing the read or write operation (signalled on the IOR or IOW lines). Finally, at time t.sub.4 the ready (RDY#) signal designates the operation is complete. (This signal is actually generated by expansion bus chip set 3 in FIG. 1, acting as the expansion bus controller.) A PC that could access large data storage by means faster than access via the expansion bus 2 would be a distinct improvement over the prior art.
The disparity of bus widths between newer CPU's and standard hard drives is another limiting factor for PC I/O operations. Generally available PC hard disk drives have data port widths of a maximum of 16 bits. New generations of CPUs, such as the Intel i486.TM. CPU, are 32-bit devices. Further, 64-bit devices are currently being implemented, e.g., the Intel Pentium.TM.. Therefore, if a 32-bit (or 64-bit) CPU wants to read or write to a conventional hard disk drive, then each 32-bit (or 64-bit) data word must be at least divided into 16-bit words, and the two (or four) 16-bit words must be sent sequentially to the hard disk drive. Therefore, there is a need to overcome this second limitation in PC data storage, the bottleneck created by data words on the larger data path of the CPU being sent to the smaller data port of the hard disk drive.